Field of the Invention
The present invention relates to an information processing apparatus comprising a programmable logic device and a method of controlling the same.
Description of the Related Art
In Japanese Patent Laid-Open No. 2013-098823, as an FPGA (Field Programmable Gate Array) configuration method, a method that is different to a method of loading configuration data from a ROM (Read Only Memory) is illustrated. Specifically, it is a method of loading configuration data from an HDD (Hard Disk Drive) into an FPGA where a CPU (Central Processing Unit) is made to be a master device. Hereinafter this method will be referred to as “a CPU master configuration” By using a CPU master configuration, it becomes possible to update FPGA processing content by replacing a file in an HDD to load without rewriting a ROM. In this way, because any FPGA can be rewritten from the CPU, it is possible to increase the number of types of processes (jobs) that an FPGA can execute more conveniently than before.
There are FPGAs that are equipped with multiple high speed ports (for example, PCI Express) that the CPU can connect to. 2 or more CPUs share this kind of FPGA, and it becomes possible to allow an acceleration of processing by each CPU using a logic circuit comprised in the FPGA. Assume that in such an FPGA-sharing configuration, a CPU accepts a job for which a shortening in processing time by using the FPGA can be expected, for example. Here, when another CPU is using the FPGA already, conventionally, the first CPU would wait for usage to become possible by the other CPU completing its usage of the FPGA. However, depending on the content of the job that the first CPU is to execute, there are cases where not waiting for the FPGA to become usable and rather executing the job itself without using the FPGA would lead to a shortening in the processing time.